1. Field of the Invention
The present invention relates to a memory testing apparatus and a memory testing method for testing a memory (IC memory) in the form of a semiconductor integrated circuit (IC), and more particularly, to an analysis for relieving a failure of a semiconductor memory.
2. Description of the Related Art
FIG. 4 shows a basic construction of a conventional memory testing apparatus of this type. The illustrated memory testing apparatus TS comprises a pattern generator 10, a waveform producing device 11, a logical comparator 12, a failure analysis memory 13, and a mask memory 14, and also includes a main controller CP for controlling operations of the memory testing apparatus TS. This main controller CP comprises a computer, and the pattern generator 10 and the logical comparator 12 are also connected to the main controller CP.
The pattern generator 10 generates, under control of the main controller PC, an address signal and a test pattern data signal to supply them to the waveform producing device 11. The waveform producing device 11 produces, based on the signals supplied thereto, an address signal and a test pattern signal having waveforms required for testing a semiconductor memory to be tested (hereinafter referred to as memory under test) MUT and applies those signals to the memory under test MUT to write the test pattern signal in each address of the memory under test MUT.
The test pattern signal written in the memory under test MUT is read out therefrom later and is supplied to the logical comparator 12 where it is compared with an expected value data signal (EXP) supplied to the logical comparator 12 from the pattern generator 10 under control of the main controller CP. If there is an anticoincidence or mismatch between both signals, the logical comparator 12 outputs a failure signal to the failure analysis memory 13, and the failure signal (failure data) is stored at an address of the failure analysis memory 13 which is specified by an address signal (not shown) supplied to the failure analysis memory 13 from the pattern generator 10. At the same time, the logical comparator 12 informs the main controller CP of the occurrence of a failure memory cell. Usually, since an address signal supplied to the memory under test MUT when the written data is read out thereof is also supplied to the failure analysis memory 13, the failure data is stored at the same address of the failure analysis memory 13 as that of the memory under test MUT.
In such a way, failure data indicating positions of failure memory cells of the memory under test MUT having occurred during one test cycle are stored in the failure analysis memory 13.
Usually, the memory testing apparatus TS is arranged to carry out function tests of a plurality of items for a memory under test MUT by changing, for example, the amplitude value of a test pattern signal, or the operation voltage applied to the memory under test MUT, thereby to detect failure memory cells of that memory. In this case, failure cell information generated in each function test is stored in the failure analysis memory 13, and with reference to the stored data, an analysis of relieving a failure (hereinafter referred to as failure relieving analysis) of the memory under test is carried out, that is, a decision for determining whether it is possible to relieve the memory under test or not possible is rendered.
A predetermined length of time is required for performing a failure relieving analysis of a memory. If a failure relieving analysis is performed for each function test, a considerably long time is required in total. Therefore, the failure relieving analysis must be performed at the required minimum.
Consequently, as shown in FIG. 4, in the prior art memory testing apparatus, a mask memory 14 is provided in addition to the failure analysis memory 13. Information of failure memory cells which have been determined as failure memory cells in the previous function test is stored in this mask memory 14. In the next function test, a mask data (MASK) for inhibiting the logical comparator 12 from performing a logical comparison operation on the same memory cell position as the failure memory cell position which is already stored in the mask memory 14 is supplied to the logical comparator 12. In the case in which the logical comparator 12 does not detect a new failure memory cell due to this masking of the failure memory cell positions, the logical comparator 12 does not inform the main controller CP of an occurrence of a failure memory cell. Thus, the main controller CP determines "there is no failure memory cell detected" and controls the operation of the memory testing apparatus TS such that the failure relieving analysis of the memory is omitted and the control operation jumps to the next function test.
The control operation of the main controller CP will be further explained with reference to a flow chart shown in FIG. 5.
FIG. 5 exemplarily shows three consecutive function test routines consisting of a first function test routine LU1, a second function test routine LU2 and a third function test routine LU3, and storage states of failure memory cell information in the failure analysis memory 13 and the mask memory 14 in each of the function test routines LU1-LU3.
First, at the starting time (START) of a first function test of the first function test routine LU1, the storage contents of the failure analysis memory 13 and the mask memory 14 are cleared, and all the stored data are erased.
Next, the first function test of step SP1 is immediately performed. When a failure signal indicating a discordance is outputted from the logical comparator 12 during this function test, a failure data of, for example, logical "1" indicating a failure memory cell is stored in an address of the failure analysis memory 13 which is the same address of the memory under test MUT where the failure memory cell exists. In the example of FIG. 5, there is shown a case in which failures occurred in three memory cells of a memory under test.
Even if a failure occurs in only one memory cell of the memory under test during the first function test in step SP1, the logical comparator 12 informs the main controller CP of the failure occurrence. Thus, the main controller CP recognizes that a failure memory cell is detected during the first function test. Since the main controller CP recognizes that a failure memory cell has been detected in the first function test routine LU1, a failure of the memory cell is determined based on the recognition data in step SP2 for determining pass/failure of a memory cell and then a memory failure relieving analysis of step SP3 is performed.
In step SP3 for a memory failure relieving analysis, the number of failure memory cells stored in the failure analysis memory 13 is counted and a determination is made to see if the failure memory cells counted can be replaced by alternate memory cells. If the replacement is possible, the control operation proceeds to the second function test routine LU2.
In the second function test routine LU2, the stored data in the failure analysis memory 13 are transferred first to the mask memory 14 before performing the second function test of step SP4 and the position information of the failure memory cells detected in the first function test is copied to the mask memory 14.
When the second function test of step SP4 is performed, the storage contents of the mask memory 14 are supplied to the logical comparator 12 as mask data and the logical comparator 12 is inhibited from performing logical comparison operations on the same memory cell positions as the failure memory cell positions (three memory cells in the illustrated example) the information of which is already stored in the mask memory 14. Therefore, if there is no failure detected during the second function test of step SP4 in the memory cells other than the failure memory cells detected in the former test, the logical comparator 12 does not detect any failure memory cell. Consequently, the main controller CP concludes that there is "no memory cell determined to be a failure memory cell" in the second function test. As a result, since the number of failure memory cells is equal to the result of the first function test, the pass/failure determination process performed in step SP5 determines that the memory under test is pass. Then the control operation proceeds to the next third function test routine LU3 without performing step SP6 for memory failure relieving analysis.
In the third function test routine LU3 illustrated in FIG. 5, there is shown a case in which two failure memory cells are newly detected in the memory under test during the third function test of step SP7. Since the main controller CP recognizes the occurrence of failure memory cells based on the detection of the new failure memory cells, the memory under test is determined to be a failure memory in step SP8 after the third function test of step SP7 is completed, and then step SP9 for memory failure relieving analysis is performed.
As mentioned above, in the prior art memory testing apparatus, information of memory cells determined to be failure memory cells in the function tests performed in the past is stored in the mask memory 14. This information of the failure memory cell positions stored in the mask memory 14 is supplied to the logical comparator 12 so that the comparison operations of the logical comparator 12 on those memory cells are masked (inhibited). As a result, since the logical comparison operations are not performed for the positions of the memory cells determined to be failure memory cells in the past, no failure signal is generated even if, in the subsequent function tests, a failure memory cell exists at the same position as that of the memory cell determined to be a failure memory cell in the past. That is, since a failure relieving analysis is performed only when new failure memory cells are detected, the number of times that failure relieving analysis operations are performed can be reduced and the test time of a memory under test can be reduced.
However, there is a drawback in the construction of the conventional memory testing apparatus that a mask memory 14 is required in addition to a failure analysis memory 13. That is, the failure analysis memory 13 has a large storage capacity and the mask memory 14 requires the same storage capacity as that of the failure analysis memory 13. Therefore, an extra memory having a large storage capacity must be added and hence there is a drawback that the manufacturing cost of the memory testing apparatus becomes considerably high.